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HY5DU283222Q
128M(4Mx32) DDR SDRAM
HY5DU283222Q
This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.9/ Nov. 01
HY5DU283222Q
Revision History
6. Revision 0.9 (Dec. 01)
1) Power dissipation SPEC. changed from 1W to 2W 2) 200MHz IDD4 SPEC changed from 370mA to 300mA 3) Output Load circuit updated
5. Revision 0.8 (Nov. 01)
1) tRCD of 3clocks at 183/200MHz at non-pingpong pattern defined 2) tCK Max of 183/200MHz part changed from 7ns to 8ns
4. Revision 0.7 (Oct. 01)
1) Changed some AC parameters a) tQHS : Changed from 0.75ns to 0.45ns at 200/183Mhz b) tDS/tDH : Changed from 0.5ns to 0.45ns
3. Revision 0.6 (Oct. 01)
1) Changed VIH/VIL from Vref +/- 0.35V to Vref +/- 0.45V 2) Change tCK_max from 5.5ns to 6ns at 250/222Mhz and from 10ns to 7ns at 200/183Mhz
2. Revision 0.5 (Aug. 01)
1) Removed 166Mhz part from speed bin 2) Defined IDD specification 3) Defined AC parameters of 250Mhz part 4) Changed Pin Capacitance a) Input Clock capacitance : Changed from 2/3pF to 1.7/2.7pF (min/max) b) All other Input-only pins capacitance : Changed from 2/3pF to 1.7/2.7pF (min/max) c) Input/Output capacitance (DQ, DQS, DM) : Changed from 4/5pF to 3.7/4.7pF (min/max) 5) Changed some AC parameters a) tIS/tIH : Changed from 0.9ns to 1.0ns b) tDS/tDH : Changed from 0.45ns to 0.5ns 6) Changed VIH/VIL from Vref +/- 0.31V to Vref +/- 0.35V
1. Revision 0.4 (Jun. 01)
1) Changed some AC parameters a) tAC : Changed from 0.7ns to 0.9ns b) tDQSCK : Changed from 0.6ns to 0.7ns c) tRCD/tRP : Changed from 4clks to 5clks at 222Mhz and from 3clks to 4clks at 200/183Mhz
Rev. 0.9 / Nov. 01
2
HY5DU283222Q DESCRIPTION
The Hynix HY5DU283222Q is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the point-to-point applications which requires high bandwidth. The Hynix 4Mx32 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2.
FEATURES
* * * * * * * VDD, VDDQ = 2.5V 5% All inputs and outputs are compatible with SSTL_2 interface JEDEC standard 20mm x 14mm 100pin LQFP with 0.65mm pin pitch Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) Data(DQ) and Write masks(DM) latched on the both rising and falling edges of the data strobe * * * * * * * * * All addresses and control inputs except Data, Data strobes and Data masks latched on the rising edges of the clock Write mask byte controls by DM (DM0 ~ DM3) Programmable /CAS Latency 3 and 4 supported Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode Internal 4 bank operations with single pulsed /RAS tRAS Lock-Out function supported Auto refresh and self refresh supported 4096 refresh cycles / 32ms Half strength and Matched Impedance driver option controlled by EMRS
*
ORDERING INFORMATION
Part No. HY5DU283222Q-4 HY5DU283222Q-45 HY5DU283222Q-5 HY5DU283222Q-55 VDD/VDDQ = 2.5V Power Supply Clock Frequency 250MHz 222MHz 200MHz 183MHz Max Data Rate 500Mbps/pin 444Mbps/pin 400Mbps/pin 366Mbps/pin SSTL_2 20mm x 14mm 100pin LQFP interface Package
Rev. 0.9 / Nov. 01
3
HY5DU283222Q
PIN CONFIGURATION
VDD VDDQ
NC VDDQ VSS
DQ2 VSSQ
NC VSSQ
DQ31 DQ30 84 83
VSSQ 82
DQ0
100
99 98
97
96 95
94
93 92
91
90 89 88
NC
87
86
85
DQ3 VDDQ DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ DQ16 DQ17 VSSQ DQ18 DQ19 VDDQ VDD VSS DQ20 DQ21 VSSQ DQ22 DQ23 VDDQ DM0 DM2 /WE /CAS /RAS /CS BA0 BA1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
81
DQ29
DQ1
DQS
NC
NC NC
TOP VIEW
20mm x 14mm 100Pin QFP 0.65mm Pitch
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 45 46 47 48 49 50
DQ28 VDDQ DQ27 DQ26 VSSQ DQ25 DQ24 VDDQ DQ15 DQ14 VSSQ DQ13 DQ12 VDDQ VSS VDD DQ11 DQ10 VSSQ DQ9 DQ8 VDDQ VREF DM3 DM1 CLK /CLK CKE DSF, MCL A8/AP
41 42
38 39
40
36 37
43 44
A9 VSS
NC NC
A3 VDD A10
A11
NC
NC NC NC NC
A2
ROW and COLUMN ADDRESS TABLE
Items
Organization Row Address Column Address Bank Address Auto Precharge Flag Refresh
A0
4Mx32
1M x 32 x 4banks A0 ~ A11 A0 ~ A7 BA0, BA1 A8 4K
Rev. 0.9 / Nov. 01
A5
A6 A7
A1
A4
4
HY5DU283222Q
PIN DESCRIPTION
PIN CK, /CK TYPE Input DESCRIPTION Clock: CK and /CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of /CK. Output (read) data is referenced to the crossings of CK and /CK (both directions of crossing). Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE must be maintained high throughout READ and WRITE accesses. Input buffers, excluding CK, /CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW level after Vdd is applied. Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All commands are masked when CS is registered high. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRECHARGE command is being applied. Address Inputs: Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. A8 is sampled during a precharge command to determine whether the PRECHARGE applies to one bank (A8 LOW) or all banks (A8 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op code during a MODE REGISTER SET command. BA0 and BA1 define which mode register is loaded during the MODE REGISTER SET command (MRS or EMRS). Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being entered. Input Data Mask: DM(0~3) is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. DM0 corresponds to the data on DQ0-Q7; DM1 corresponds to the data on DQ8-Q15; DM2 corresponds to the data on DQ16-Q23; DM3 corresponds to the data on DQ24-Q31. Data Strobe: Output with read data, input with write data. Edge aligned with read data, centered in write data. Used to capture write data. Data input / output pin : Data Bus Power supply for internal circuits and input buffers. Power supply for output buffers for noise immunity. Reference voltage for inputs for SSTL interface. No connection.
CKE
Input
/CS
Input
BA0, BA1
Input
A0 ~ A11
Input
/RAS, /CAS, /WE
Input
DM0 ~ DM3
Input
DQS DQ0 ~ DQ31 VDD/VSS VDDQ/VSSQ VREF NC
I/O I/O Supply Supply Supply NC
Rev. 0.9 / Nov. 01
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HY5DU283222Q
FUNCTIONAL BLOCK DIAGRAM
4Banks x 1Mbit x 32 I/O Double Data Rate Synchronous DRAM
Write Data Register 2-bit Prefetch Unit 64 CLK /CLK CKE /CS /RAS /CAS /WE DM(0~3) Bank Control Command Decoder 1Mx32/Bank0 Sense AMP 1Mx32 /Bank1 1Mx32 /Bank2 1Mx32 /Bank3 Mode Register Row Decoder 64
32
Input Buffer
DS
2-bit Prefetch Unit
Output Buffer
32
DQ[0:31]
Column Decoder
A0-11 BA0,BA1
Address Buffer
DQS Column Address Counter CLK_DLL DS Data Strobe Transmitter Data Strobe Receiver
CLK, /CLK
DLL Block
Mode Register
Rev. 0.9 / Nov. 01
6
HY5DU283222Q
SIMPLIFIED COMMAND TRUTH TABLE
Command Extended Mode Register Set Mode Register Set Device Deselect No Operation Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Read Burst Stop Auto Refresh Entry Self Refresh Exit CKEn-1 H H H H H CKEn X X X X X CS L L H L L L RAS L L X H L H CAS L L X H H L WE L L X H H H CA RA L H L H H L X X
ADDR
A8/ AP OP code OP code X
BA
Note 1,2 1,2 1
V V
1 1 1,3 1 1,4 1,5 1 1 1 1
H
X
L
H
L
L
CA
V X V
H H H H L
X X H L H
L L L L H L H L H L H L
L H L L X H X H X H X V X
H H L L X H X H X H X V
L L H H X H X H X H X V
X
X
1 1
Entry Precharge Power Down Mode Exit
H
L
X
1 1 1 1
L
H
Active Power Down Mode
Entry Exit
H L
L H
X
1 1
( H=Logic High Level, L=Logic Low Level, X=Don' Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation ) t Note : 1. DM(0~3) states are Don' Care. Refer to below Write Mask Truth Table. t 2. OP Code(Operand Code) consists of A0~A11 and BA0~BA1 used for Mode Register setting during Extended MRS or MRS. Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP period from Prechagre command. 3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented to activated bank until CK(n+BL/2+tRP). 4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time (tWR) is needed to guarantee that the last data has been completely written. 5. If A8/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be precharged.
Rev. 0.9 / Nov. 01
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HY5DU283222Q
WRITE MASK TRUTH TABLE
Function Data Write Data-In Mask CKEn-1 H H CKEn X X /CS, /RAS, /CAS, /WE X X DM(0~3) L H
ADDR
A8/ AP X X
BA
Note
1,2 1,2
Note : 1. Write Mask command masks burst write data with reference to DQS(Data Strobes) and it is not related with read data. 2. DM0 corresponds to the data on DQ0-Q7; DM1 corresponds to the data on DQ8-Q15; DM2 corresponds to the data on DQ16-Q23; DM3 corresponds to the data on DQ24-Q31.
Rev. 0.9 / Nov. 01
8
HY5DU283222Q
OPERATION COMMAND TRUTH TABLE - I
Current State /CS H L L L IDLE L L L L L H L L L ROW ACTIVE L L L L L H L L L READ L L L L L H L WRITE L L L Rev. 0.9 / Nov. 01 /RAS X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H H H /CAS X H H L L H H L L X H H L L H H L L X H H L L H H L L X H H L L /WE X H L H L H L H L X H L H L H L H L X H L H L H L H L X H L H L Address X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP Command DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP Action NOP or power down3 NOP or power down3 ILLEGAL4 ILLEGAL4 ILLEGAL4 Row Activation NOP Auto Refresh or Self Refresh5 Mode Register Set NOP NOP ILLEGAL4 Begin read : optional AP6 Begin write : optional AP6 ILLEGAL4 Precharge7 ILLEGAL11 ILLEGAL11 Continue burst to end Continue burst to end Terminate burst Term burst, new read:optional AP 8 ILLEGAL ILLEGAL4 Term burst, precharge ILLEGAL11 ILLEGAL11 Continue burst to end Continue burst to end ILLEGAL4 Term burst, new read:optional AP 8 Term burst, new write:optional AP 9
HY5DU283222Q
OPERATION COMMAND TRUTH TABLE - II
Current State /CS L WRITE L L L H L L READ WITH AUTOPRECHARGE L L L L L L H L L WRITE AUTOPRECHARGE L L L L L L H L L L PRECHARGE L L L L L /RAS L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L /CAS H H L L X H H L L H H L L X H H L L H H L L X H H L L H H L L /WE H L H L X H L H L H L H L X H L H L H L H L X H L H L H L H L Address BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE Command ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS Action ILLEGAL4 Term burst, precharge ILLEGAL11 ILLEGAL11 Continue burst to end Continue burst to end ILLEGAL ILLEGAL10 ILLEGAL10 ILLEGAL4,10 ILLEGAL4,10 ILLEGAL11 ILLEGAL11 Continue burst to end Continue burst to end ILLEGAL ILLEGAL10 ILLEGAL10 ILLEGAL4,10 ILLEGAL4,10 ILLEGAL11 ILLEGAL11 NOP-Enter IDLE after tRP NOP-Enter IDLE after tRP ILLEGAL4 ILLEGAL4,10 ILLEGAL4,10 ILLEGAL4,10 NOP-Enter IDLE after tRP ILLEGAL11 ILLEGAL11
Rev. 0.9 / Nov. 01
10
HY5DU283222Q
OPERATION COMMAND TRUTH TABLE - III
Current State /CS H L L L ROW ACTIVATING L L L L L H L L L WRITE RECOVERING L L L L L H L L WRITE RECOVERING WITH AUTOPRECHARGE L L L L L L H L REFRESHING L L /RAS X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H H /CAS X H H L L H H L L X H H L L H H L L X H H L L H H L L X H H L /WE X H L H L H L H L X H L H L H L H L X H L H L H L H L X H L H Address X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP Command DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP Action NOP - Enter ROW ACT after tRCD NOP - Enter ROW ACT after tRCD ILLEGAL4 ILLEGAL4,10 ILLEGAL4,10 ILLEGAL4,9,10 ILLEGAL4,10 ILLEGAL11 ILLEGAL11 NOP - Enter ROW ACT after tWR NOP - Enter ROW ACT after tWR ILLEGAL4 ILLEGAL ILLEGAL ILLEGAL4,10 ILLEGAL4,11 ILLEGAL11 ILLEGAL11 NOP - Enter precharge after tDPL NOP - Enter precharge after tDPL ILLEGAL4 ILLEGAL4,8,10 ILLEGAL4,10 ILLEGAL4,10 ILLEGAL4,11 ILLEGAL11 ILLEGAL11 NOP - Enter IDLE after tRC NOP - Enter IDLE after tRC ILLEGAL11 ILLEGAL11
Rev. 0.9 / Nov. 01
11
HY5DU283222Q
OPERATION COMMAND TRUTH TABLE - IV
Current State /CS L L WRITE L L L H L L L MODE REGISTER ACCESSING L L L L L /RAS H L L L L X H H H H L L L L /CAS L H H L L X H H L L H H L L /WE L H L H L X H L H L H L H L Address BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE Command WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS Action ILLEGAL11 ILLEGAL11 ILLEGAL11 ILLEGAL11 ILLEGAL11 NOP - Enter IDLE after tMRD NOP - Enter IDLE after tMRD ILLEGAL11 ILLEGAL11 ILLEGAL11 ILLEGAL11 ILLEGAL11 ILLEGAL11 ILLEGAL11
Note : 1. H - Logic High Level, L - Logic Low Level, X - Don' Care, V - Valid Data Input, t BA - Bank Address, AP - AutoPrecharge Address, CA - Column Address, RA - Row Address, NOP - NO Operation. 2. All entries assume that CKE was active(high level) during the preceding clock cycle. 3. If both banks are idle and CKE is inactive(low level), then in power down mode. 4. Illegal to bank in specified state. Function may be legal in the bank indicated by Bank Address(BA) depending on the state of that bank. 5. If both banks are idle and CKE is inactive(low level), then self refresh mode. 6. Illegal if tRCD is not met. 7. Illegal if tRAS is not met. 8. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 9. Illegal if tRRD is not met. 10. Illegal for single bank, but legal for other banks in multi-bank devices. 11. Illegal for all banks.
Rev. 0.9 / Nov. 01
12
HY5DU283222Q
CKE FUNCTION TRUTH TABLE
Current State CKEn1 H L L SELF REFRESH1 L L L L H L L POWER DOWN 2 L L L L H H H H ALL BANKS IDLE4 H H H H L H ANY STATE OTHER THAN ABOVE H L L CKEn X H H H H H L X H H H H H L H L L L L L L L L H L H L /CS X H L L L L X X H L L L L X X L H L L L L L X X X X X /RAS X X H H H L X X X H H H L X X L X H H H L L X X X X X /CAS X X H H L X X X X H H L X X X L X H H L H L X X X X X /WE X X H L X X X X X H L X X X X H X H L X X L X X X X X /ADD X X X X X X X X X X X X X X X X X X X X X X X X X X X Action INVALID Exit self refresh, enter idle after tSREX Exit self refresh, enter idle after tSREX ILLEGAL ILLEGAL ILLEGAL NOP, continue self refresh INVALID Exit power down, enter idle Exit power down, enter idle ILLEGAL ILLEGAL ILLEGAL NOP, continue power down mode See operation command truth table Enter self refresh Exit power down Exit power down ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP See operation command truth table ILLEGAL5 INVALID INVALID
Note : When CKE=L, all DQ and DQS must be in Hi-Z state. 1. CKE and /CS must be kept high for a minimum of 200 stable input clocks before issuing any command. 2. All command can be stored after 2 clocks from low to high transition of CKE. 3. Illegal if CK is suspended or stopped during the power down mode. 4. Self refresh can be entered only from the all banks idle state. 5. Disabling CK may cause malfunction of any bank which is in active state.
Rev. 0.9 / Nov. 01
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HY5DU283222Q
SIMPLIFIED STATE DIAGRAM
MODE REGISTER SET
MRS IDLE
SREF SREX SELF REFRESH
PDEN PDEX POWER DOWN POWER DOWN PDEX PDEN BST BANK ACTIVE ACT AREF AUTO REFRESH
READ WRITE READAP WRITE WRITEAP PRE(PALL) WRITE WITH AUTOPRECHARGE READ READAP WITH AUTOPRECHARGE WRITEAP READ READ
WRITE PRE(PALL) PRE(PALL) PRECHARGE
POWER-UP
Command Input Automatic Sequence
POWER APPLIED
Rev. 0.9 / Nov. 01
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HY5DU283222Q
POWER-UP SEQUENCE AND DEVICE INITIALIZATION
DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power must first be applied to VDD, then to VDDQ, and finally to VREF (and to the system VTT). VTT must be applied after VDDQ to avoid device latch-up, which may cause permanent damage to the device. VREF can be applied anytime after VDDQ, but is expected to be nominally coincident with VTT. Except for CKE, inputs are not recognized as valid until after VREF is applied. CKE is an SSTL_2 input, but will detect an LVCMOS LOW level after VDD is applied. Maintaining an LVCMOS LOW level on CKE during power-up is required to guarantee that the DQ and DQS outputs will be in the High-Z state, where they will remain until driven in normal operation (by a read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200us delay prior to applying an executable command. Once the 200us delay has been satisfied, a DESELECT or NOP command should be applied, and CKE should be brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a EXTENDED MODE REGISTER SET command should be issued for the Extended Mode Register, to enable the DLL, then a MODE REGISTER SET command should be issued for the Mode Register, to reset the DLL, and to program the operating parameters. 200 clock cycles are required between the DLL reset and any command. During the 200 cycles of CK, for DLL locking, executable commands are disallowed (a DESELECT or NOP command must be applied). After the 200 clock cycles, a PRECHARGE ALL command should be applied, placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a MODE REGISTER SET command for the Mode Register, with the reset DLL bit deactivated (i.e. to program operating parameters without resetting the DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal operation. 1. Apply power - VDD, VDDQ, VTT, VREF in the following power up sequencing and attempt to maintain CKE at LVCMOS low state. (All the other input pins may be undefined.) * VDD and VDDQ are driven from a single power converter output. * VTT is limited to 1.44V (reflecting VDDQ(max)/2 + 50mV VREF variation + 40mV VTT variation. * VREF tracks VDDQ/2. * A minimum resistance of 42 Ohms (22 ohm series resistor + 22 ohm parallel resistor - 5% tolerance) limits the input current from the VTT supply into any pin. * If the above criteria cannot be met by the system design, then the following sequencing and voltage relationship must be adhered to during power up. Votage description VDDQ VTT VREF 2. 3. 4. 5. 6. Sequencing After or with VDD After or with VDDQ After or with VDDQ Voltage relationship to avoid latch-up < VDD + 0.3V < VDDQ + 0.3V < VDDQ + 0.3V
Start clock and maintain stable clock for a minimum of 200usec. After stable power and clock, apply NOP condition and take CKE high. Issue Extended Mode Register Set (EMRS) to enable DLL. Issue Mode Register Set (MRS) to reset DLL and set device to idle state with bit A8=High. (An additional 200 cycles of clock are required for locking DLL) Issue Precharge commands for all banks of the device.
15
Rev. 0.9 / Nov. 01
HY5DU283222Q
7. 8.
Issue 2 or more Auto Refresh commands. Issue a Mode Register Set command to initialize the mode register with bit A8 = Low.
Power-Up Sequence
VDD VDDQ VTT VREF
tVTD
/CLK CLK

tIS tIH
CKE CMD DM(0~3) ADDR A8 BA0,BA1

NOP
PRE
EMRS
MRS
NOP
PRE
AREF
MRS
CODE
CODE
CODE
CODE
CODE
CODE
CODE
CODE
CODE

DQS DQ' s
T=200usec
tRP
tMRD
200 cycles of CK*
tRP
tRFC
Power up VDD and CK stable
EMRS Set Precharge All
MRS Set Reset DLL (with A8=H)
Precharge All
2 or more Auto Refresh
MRS Set (with A8=L)
*200 cycles of CK are required (for DLL locking) before any executable command can be applied.
Rev. 0.9 / Nov. 01
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HY5DU283222Q
MODE REGISTER SET (MRS)
The mode register is used to store the various operating modes such as /CAS latency, addressing mode, burst length, burst type, test mode, DLL reset. The mode register is program via MRS command. This command is issued by the low signals of /RAS, /CAS, /CS, /WE and BA0. This command can be issued only when all banks are in idle state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. Two cycles are required to write the data in mode register. During the the MRS cycle, any command cannot be issued. Once mode register field is determined, the information will be held until resetted by another MRS command.
BA1 0
BA0 0
A11
A10 RFU
A9
A8 DR
A7 TM
A6
A5
A4
A3 BT
A2
A1
A0
CAS Latency
Burst Length
BA0 0 1
MRS Type MRS
A7
Test Mode Normal Vendor test mode A2 A1 A0 Sequential 0 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Reserved 2 4 8 Reserved Reserved Reserved Reserved Interleave Reserved 2 4 8 Reserved Reserved Reserved Reserved
0 EMRS 1
Burst Length
A8 0 1
DLL Reset No Yes
A6 0 0 0 0 1 1 1 1
A5 0 0 1 1 0 0 1 1
A4 0 1 0 1 0 1 0 1
CAS Latency Reserved Reserved Reserved 3 4 Reserved Reserved Reserved A3 0 1
0 1 1 1 1
Burst Type Sequential Interleave
Rev. 0.9 / Nov. 01
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HY5DU283222Q
BURST DEFINITION
Burst Length 2 Starting Address (A2,A1,A0) XX0 XX1 X00 4 X01 X10 X11 000 001 010 8 011 100 101 110 111 Sequential 0, 1 1, 0 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1, 2 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 0, 1, 2, 3, 4 6, 7, 0, 1, 2, 3, 4, 5 0, 1, 2, 3, 4, 5, 6, 7 Interleave 0, 1 1, 0 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0
BURST LENGTH & TYPE
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst length determines the maximum number of column locations that can be accessed for a given Read or Write command. Burst lengths of 2, 4 or 8 locations are available for both the sequential and the interleaved burst types. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai when the burst length is set to four and by A3-Ai when the burst length is set to eight (where Ai is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both Read and Write bursts. Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Burst Definitionon Table
Rev. 0.9 / Nov. 01
18
HY5DU283222Q
CAS LATENCY
The Read latency or CAS latency is the delay in clock cycles between the registration of a Read command and the availability of the first burst of output data. The latency can be programmed 3 or 4 clocks. If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident with clock edge n +m. Reserved states should not be used as unknown operation or incompatibility with future versions may result.
DLL RESET
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time the DLL is enabled, 200 clock cycles must occur to allow time for the internal clock to lock to the externally applied clock before an any command can be issued.
OUTPUT DRIVER IMPEDANCE CONTROL
The HY5DU283222Q supports both Half strength driver and Matched impedance driver, intended for lighter load and/ or point-to-point environments. Half strength driver is to define about 50% of Full drive strength which is specified to be SSTL_2, Class II, and Matched impedance driver, about 30% of Full drive strength.
Rev. 0.9 / Nov. 01
19
HY5DU283222Q
EXTENDED MODE REGISTER SET (EMRS)
The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functions include DLL enable/disable, output driver strength selection(optional). These functions are controlled via the bits shown below. The Extended Mode Register is programmed via the Mode Register Set command ( BA0=1 and BA1=0) and will retain the stored information until it is programmed again or the device loses power. The Extended Mode Register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements will result in unspecified operation.
BA1 0 BA0 1 A11 A10 A9 RFU* A8 A7 A6 DS A5 A4 A3 A2 A1 DS A0 DLL
RFU*
BA0 0 1
MRS Type MRS EMRS
A0 0 1
DLL enable Enable Diable
A6 0 0 1 1
A1 0 1 0 1
Output Driver Impedance Control RFU* Half RFU* Matched Impedance (Weak)
* All bits in RFU address fields must be programmed to Zero, all other states are reserved for future usage.
Rev. 0.9 / Nov. 01
20
HY5DU283222Q
ABSOLUTE MAXIMUM RATINGS
Parameter
Ambient Temperature Storage Temperature Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Voltage on VDDQ relative to VSS Output Short Circuit Current Power Dissipation Soldering Temperature Time
Symbol
TA TSTG VIN, VOUT VDD VDDQ IOS PD TSOLDER
Rating
0 ~ 70 -55 ~ 125 -0.5 ~ 3.6 -0.5 ~ 3.6 -0.5 ~ 3.6 50 2 260 10
o
Unit
oC o
C
V V V mA W C sec
Note : Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITIONS
Parameter
Power Supply Voltage Power Supply Voltage Input High Voltage Input Low Voltage Termination Voltage Reference Voltage
(TA=0 to 70oC, Voltage referenced to VSS = 0V)
Symbol
VDD VDDQ VIH VIL VTT VREF
Min
2.375 2.375 VREF + 0.15 -0.3 VREF - 0.04 0.49*VDDQ
Typ.
2.5 2.5 VREF 0.5*VDDQ
Max
2.625 2.625 VDDQ + 0.3 VREF - 0.15 VREF + 0.04 0.51*VDDQ
Unit
V V V V V V
Note
1
2
3
Note : 1. VDDQ must not exceed the level of VDD. 2. VIL (min) is acceptable -1.5V AC pulse width with 5ns of duration. 3. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of the same. Peak to peak noise on VREF may not exceed 2% of the dc value.
DC CHARACTERISTICS I
Parameter
Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage
(TA=0 to 70oC, Voltage referenced to VSS = 0V)
Symbol
ILI ILO VOH VOL
Min.
-5 -5 VTT + 0.76 -
Max
5 5 VTT - 0.76
Unit
uA uA V V
Note
1 2 IOH = -15.2mA IOL = +15.2mA
Note : 1. VIN = 0 to 3.6V, All other pins are not tested under VIN =0V. 2. DOUT is disabled, VOUT=0 to 2.7V Rev. 0.9 / Nov. 01 21
HY5DU283222Q
DC CHARACTERISTICS II (TA=0 to 70oC, Voltage referenced to VSS = 0V)
Speed Parameter Symbol Test Condition 4 Burst length=2, One bank active tRC tRC(min), IOL=0mA CKE VIL(max), tCK = min CKE VIH(min), /CS VIH(min), tCK = min, Input signals are changed one time during 2clks CKE VIL(max), tCK = min CKE VIH(min), /CS VIH(min), tCK = min, Input signals are changed one time during 2clks tCK tCK(min), IOL=0mA All banks active tRC tRFC(min), All banks active CKE 0.2V 45 5 55 Unit Note
Operating Current Precharge Standby Current in Power Down Mode Precharge Standby Current in Non Power Down Mode Active Standby Current in Power Down Mode Active Standby Current in Non Power Down Mode Burst Mode Operating Current Auto Refresh Current Self Refresh Current
IDD1
260
250
240
230
mA
1
IDD2P
30
25
20
20
mA
IDD2N
90
85
80
80
mA
IDD3P
35
30
25
25
mA
IDD3N
130
110
100
100
mA
IDD4
450
400
300
350
mA
1
IDD5 IDD6
270 3
mA mA
1,2
Note : 1. IDD1, IDD4 and IDD5 depend on output loading and cycle rates. Specified values are measured with the output open. 2. Min. of tRFC (Auto Refresh Row Cycle Time) is shown at AC CHARACTERISTICS.
Rev. 0.9 / Nov. 01
22
HY5DU283222Q
AC OPERATING CONDITIONS
Parameter
(TA=0 to 70 oC, Voltage referenced to VSS = 0V)
Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC)
Min VREF + 0.45
Max
Unit V
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals Input Differential Voltage, CK and /CK inputs Input Crossing Point Voltage, CK and /CK inputs
VREF - 0.45 0.7 0.5*VDDQ-0.2 VDDQ + 0.6 0.5*VDDQ+0.2
V V V 1 2
Note : 1. VID is the magnitude of the difference between the input level on CK and the input on /CK. 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
AC OPERATING TEST CONDITIONS
Parameter Reference Voltage Termination Voltage AC Input High Level Voltage (VIH, min) AC Input Low Level Voltage (VIL, max) Input Timing Measurement Reference Level Voltage Output Timing Measurement Reference Level Voltage Input Signal maximum peak swing Input minimum Signal Slew Rate Termination Resistor (RT) Series Resistor (RS)
(TA=0 to 70oC, Voltage referenced to VSS = 0V)
Value VDDQ x 0.5 VDDQ x 0.5 VREF + 0.45 VREF - 0.45 VREF VTT 1.5 1 50 25 30
Unit V V V V V V V V/ns pF
Output Load Capacitance for Access Time Measurement (CL)
Rev. 0.9 / Nov. 01
23
HY5DU283222Q
AC CHARACTERISTICS
Parameter
(AC operating conditions unless otherwise noted) 4 Min 60 68 40 5 Max 120K Min 63 67.5 40.5 5 45 Max 120K Min 55 50 65 35 4 3 2 2 1 4 3 2 2 6 5 0.45 0.45 -0.9 -0.7 tHPmin -tQHS tCH/L min 1.0 1.0 5 Max 120K 8 0.55 0.55 0.9 0.7 0.4 0.45 Min 60.5 55 66 38.5 4 3 2 2 1 4 3 2 2 6 5.5 0.45 0.45 -0.9 -0.7 tHPmin -tQHS tCH/L min 1.0 1.0 55
Unit Note
Symbol
Max 120K 8 0.55 0.55 0.9 0.7 0.4 0.45 ns ns ns ns CK CK CK CK CK CK CK CK CK CK ns ns CK CK ns ns ns ns ns ns ns ns 2,7 2,6 7 3 3 1 1 1
Row Cycle Time Auto Refresh Row Cycle Time Row Active Time Row Address to Column Address Delay for Read Row Address to Column Address Delay for Write Row Active to Row Active Delay Column Address to Column Address Delay Row Precharge Time Last Data-In to Precharge Delay Time (Write Recovery Time : tWR) Last Data-In to Read Command Auto Precharge Write Recovery + Precharge Time System Clock Cycle Time Clock High Level Width Clock Low Level Width Data-Out edge to Clock edge Skew DQS-Out edge to Clock edge Skew DQS-Out edge to Data-Out edge Skew Data-Out hold time from DQS Clock Half Period Data Hold Skew Factor Input Setup Time Input Hold Time CL = 4 CL = 3
tRC tRFC tRAS tRCDRD
tRCDWR tRRD tCCD tRP
3 2 1 5
-
3 2 1 5
-
tDPL tDRL tDAL
3 2 8 4 0.45 0.45 -0.9 -0.7 tHPmin -tQHS tCH/L min 1.0 1.0
6 0.55 0.55 0.9 0.7 0.4 0.6 -
3 2 8 4.5 0.45 0.45 -0.9 -0.7 tHPmin -tQHS tCH/L min 1.0 1.0
6 0.55 0.55 0.9 0.7 0.4 0.6 -
tCK tCH tCL tAC tDQSCK tDQSQ tQH tHP tQHS tIS tIH
Rev. 0.9 / Nov. 01
24
HY5DU283222Q
Parameter Write DQS High Level Width Write DQS Low Level Width Clock to First Rising edge of DQS-In Data-In Setup Time to DQS-In (DQ & DM) Data-In Hold Time to DQS-In (DQ & DM) Read DQS Preamble Time Read DQS Postamble Time Write DQS Preamble Setup Time Write DQS Preamble Hold Time Write DQS Postamble Time Mode Register Set Delay Exit Self Refresh to Any Execute Command Average Periodic Refresh Interval Note : 1. 2. 3. 4. 5. 6. 7.
Symbol tDQSH tDQSL tDQSS tDS tDH tRPRE tRPST tWPRES tWPREH tWPST tMRD tXSC tREFI
4 Min 0.4 0.4 0.75 0.45 0.45 0.7 0.4 0 1.5 0.4 2 200 Max 0.6 0.6 1.25 1.1 0.6 0.6 7.8 Min 0.4 0.4 0.75 0.45 0.45 0.8 0.4 0 1.5 0.4 2 200 -
45 Max 0.6 0.6 1.25 1.1 0.6 0.6 7.8 Min 0.4 0.4 0.75 0.45 0.45 0.8 0.4 0 1.5 0.4 2 200 -
5 Max 0.6 0.6 1.25 1.1 0.6 0.6 7.8 Min 0.4 0.4 0.75 0.45 0.45 0.8 0.4 0 1.5 0.4 2 200 -
55 Max 0.6 0.6 1.25 1.1 0.6 0.6 7.8
Unit Note
CK CK CK ns ns CK CK ns ns CK CK CK us 5 4 4
tRCD of 3 Clock at only non-pingpong pattern supported. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter. Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE. Data latched at both rising and falling edges of Data Strobes(DQS) : DQ, DM(0~3). Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS consists of tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions through the DC region must be monotonic.
8.
Rev. 0.9 / Nov. 01
25
HY5DU283222Q
CAPACITANCE
(TA=25oC, f=1MHz )
Parameter Input Clock Capacitance Input Capacitance Input / Output Capacitance CK, /CK
Pin
Symbol CCK CIN CIO
Min 1.7 1.7 3.7
Max 2.7 2.7 4.7
Unit pF pF pF
All other input-only pins DQ, DQS, DM
Note : 1. VDD = min. to max., VDDQ = 2.3V to 2.7V, VODC = VDDQ/2, VOpeak-to-peak = 0.2V 2. Pins not under test are tied to GND. 3. These values are guaranteed by design and are tested on a sample basis only.
OUTPUT LOAD CIRCUIT
VTT
RT=50
Output Zo=50 VREF
C L=30pF
Rev. 0.9 / Nov. 01
26
HY5DU283222Q
PACKAGE INFORMATION
20mm x 14mm 100pin Low Quad Flat Package
22.10(0.870) 21.90(0.862) 20.10(0.791) 19.90(0.783)
Unit:mm(inch)
1.60(0.063) 1.45(0.057) Base Plane
14.10(0.555) 13.90(0.547)
16.10(0.634) 15.90(0.626)
Detail A
Gauge Line 0.15(0.006) 0.05(0.002) 0~7 Deg
0.20(0.008) 0.09(0.004) 0.75(0.029) 0.50(0.020) 0.66(0.026) 0.45(0.018) 1.00(0.0394)REF
0.65 (0.026)TYP
0.080 (0.003)
0.38(0.015) 0.22(0.009)
Seating Plane
Detail A
All dimension in mm (inches). Notation is
MAX or typical. MIN
Rev. 0.9 / Nov. 01
27

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